Reliability and Variability Analyses in SRAM Decoder

Modern Static Random Access Memory (SRAM) systems are susceptible to reliability and variability issues. Examples of reliability and variability issues are Bias Temperature Instability (BTI) in the transistors and resistive/open interconnect defects, respectively. This paper analyzes the impacts of BTI and resistive defects independently as well as simultaneously on the SRAM decoder. First, the BTI analysis shows that the impact is strongly dependent on the selected wordline, transistor location, addressing scheme and can cause up to 14.27% additional delay to the address selection. Second, for resistive defects analysis, it shows that the pull-up and pull-down resistances can cause up to 23.65% and 16.95% additional delay, respectively. Finally, it shows that BTI impact accumulates with that of the resistances, resulting in an additional delay of up to 34.36% to the address selection of the decoder.